The present invention relates to techniques for increasing operation speed of semiconductor integrated circuit devices and semiconductor integrated circuit systems.
In recent years, the integration degrees of semiconductor integrated circuit devices and semiconductor integrated circuit systems have increased and power consumption thereof have been reduced with miniaturization of semiconductor elements such as transistors mounted thereon. However, with the increase of integration degree and the reduction of power consumption, through current (leakage current) in a semiconductor integrated circuit has a greater influence on power consumption of a system.
To reduce through current, a technique for changing the timing of switching between transistors is disclosed in, for example, Japanese Unexamined Patent Publication (Kokai) No. 63-169120.
In this conventional technique, the timing of switching is set at the design stage. Therefore, a margin is previously estimated when the timing of switching is set. However, if this margin is too large, operation speed might decrease.